One form of Digital-to-Analog Converter (DAC) uses a resistor string in which a set of resistors are connected in series between two voltages to form a voltage divider in which the nodes that connect resistors form tap points that can be accessed to generate an output voltage. The tap points are selected using switches based on the value of a digital input signal (e.g., a digital word).
The basic resistor string DAC described above has several advantages. It is relatively simple to implement. The output linearity is dominated by the matching of resistor ratios (by appropriately selecting the resistors, the output of the DAC can be made to change linearly with the input). The resistor string DAC also provides a reasonable trade-off between power dissipation and speed. The output is also inherently monotonic.
The resistor string DAC suffers from a number of drawbacks that arise when the hardware required for constructing the DAC is scaled to increase the resolution of the DAC. For example, when the resolution is increased, the resistor count (and, hence, the required area for a given accuracy) increases exponentially. Additionally, the switch count also increases exponentially. Switches also contribute to area requirements, but more importantly, have parasitic capacitance that also increases along with the switch count.
Variations of the basic resistor string DAC have been proposed that purport to overcome some of the above mentioned disadvantages. One variation uses a technique known as segmentation, which divides the input word into several (typically two) sub-words of decreasing weight, thereby keeping the original resolution provided by the complete input word. The most significant sub-word is applied as input to a primary sub-DAC and the remaining sub-words are applied as input to one or more secondary sub-DACs. The outputs of the individual sub-DACs are combined to generate the analog output of the overall DAC. Specifically, the overall area is reduced by dividing the total resolution N into n sub-DACs of smaller resolution (N being the sum of the resolutions of the individual sub-DACs) and generating the analog output VOUT as the sum of n weighted analog voltages provided by the n sub-DACs.
FIG. 1 is a schematic of an architecture known as a buffered resistor string DAC, which includes a tap voltage generator 10, a tap selector 12 and an output stage 14. The tap voltage generator 10 includes a resistor string 15. The taps of the resistor string 15 can be selectively connected to a buffer in the output stage 14 to obtain a buffered analog representation VOUT of a digital input word dIN. The selective connection of the taps is performed by decoding the digital input word dIN at the tap selector 12. Typically, the buffer is an operational amplifier configured in non-inverting configuration with resistive negative feedback to accurately provide the desired gain G, as shown in FIG. 1.
The relationship between the gain resistors RF and RG that implement the negative feedback loop is:RF/RG=G−1  (1)
In FIG. 1, because there is only one level of segmentation, the architecture is limited by the same disadvantages discussed above in connection with the basic resistor string DAC. That is, in order to increase the DAC resolution, it is necessary to add many resistors in series to the resistor string.
Several architectures using a voltage segmented DAC based on resistive strings have been proposed. The majority are based on interpolating the voltage drop across the elements of a coarse resistor string by coupling a fine resistor string between the terminals of such elements.
In U.S. Pat. No. 4,543,560 active buffers are used to couple a fine string to the elements of a coarse string without loading the coarse string. The non-idealities of the buffers placed between both resistor strings significantly deteriorate the dynamic performance and, potentially, the linearity of the output because of the offset of the buffers.
In U.S. Pat. No. 5,703,588 an interpolating resistor string DAC includes a current source and sink of appropriate values connected to the ends of the fine resistor string to eliminate its loading. This architecture not only requires resistors and current matching to obtain a competitive linearity, but also a particular relationship must be satisfied between the value of the currents and the resistors; hence, the implementation complexity is significantly increased. To generate the required current, an active buffer is used to force a voltage through a resistor which is conveniently sized, thus obtaining the desired current. The static non-idealities (especially the offset) of the buffer will cause an error in the current and, hence, nonlinearity at the output of the DAC.
In U.S. Pat. No. 5,969,657 an interpolating resistor string DAC does not include any circuitry to prevent the loading of the coarse string. By removing one of the elements of the fine resistor string, the loading of the coarse string is used, along with the impedance of the turned on coarse tap selection switches (which are sized to obtain a desired value) to obtain 1 LSB step when the coupled element of the coarse resistor string changes to the following element.
In the architecture described in U.S. Pat. No. 5,969,657 the linearity is dominated by the value of the switch-on impedance of the coarse tap selection switches. To obtain a reasonable margin for the variation of this parameter (that is sensitive to the voltage variation through the coarse resistor string, to process variations, and to temperature drift), a relatively big ratio between the elements of the coarse resistor string and the fine resistor string is required. The result is a fine resistor string with equivalent impedance much bigger than that of the elements of the coarse resistor string, in which the fine resistor string will be floating during code transitions. Consequently, a severely reduced fraction of the active current flows through the fine resistor string and the impact of the leakage current on the integral non-linearity (INL) is significant. This fact, in addition to the relatively big switch area required (which involves big parasitic capacitance), significantly deteriorates the dynamic performance (especially the glitch area).
In U.S. Pat. No. 6,914,547 a generalization of the architecture described above in connection with U.S. Pat. No. 5,969,657 is presented, where a third level of segmentation is introduced by the same technique. The advantages are the same as those featured by the previous architecture (with a greater area saving), but the disadvantages are significantly increased.
In U.S. Pat. No. 5,396,245 differential transconductance stages are used to add and amplify some coarse voltages and a fine voltage, but the DAC is restricted to two levels of segmentation. In this approach, matching between the transconductance of each stage is required.
In both U.S. Pat. Nos. 6,486,818 and 6,617,989 a coarse voltage and a fine current are added to generate the DAC output. In particular, a resistor string is used to form a first voltage that is essentially a coarse analog approximation of the most significant part of the digital input. A current proportional to the least significant part of the digital input is combined with the coarse voltage to generate the final output of the overall DAC. The implementations in these two patents can be viewed as an improvement over the basic buffered resistor string DAC in FIG. 1. Both patents only contemplate the combination of a coarse voltage with a single current and, hence, more than two levels of segmentation are not directly feasible without a performance tradeoff. In addition, the preferred embodiments for generating the current in each of these patents include an array of matched current sources. These current sources are defined by a circuit which includes an active buffer. Any offset error introduced by this buffer will produce non-linearity.